The present invention relates in general to data processing systems, and in particular, to bus systems with independent read and write data buses.
Recent advances in silicon densities now allow for the integration of numerous functions onto a single silicon chip. With this increased density, peripherals formally attached to the processor at the card level are now integrated onto the same die as the processor. As a result, chip designers must now address issues traditionally handled by the system designer. In particular, the on-chip buses used in such system-on-a-chip (SOC) designs must be sufficiently flexible and robust in order to support a wide variety of embedded system needs.
The IBM Blue logic core program, for example, provides the framework to efficiently realize complex system-on-a-chip designs. Typically, an SOC contains numerous functional blocks representing a very large number of logic gates. Designs such as these are best realized through a macro-based approach. Macro-based designs provide numerous benefits during logic entry and verification, but the ability to reuse intellectual property is often the most significant benefit. From generic serial ports to complex memory controllers and processor cores, each SOC generally requires the use of common macros.
Many single chip solutions used in applications today are designed as custom chips, each with their own internal architecture. Logical units within such a chip are often difficult to extract and reuse in different applications. As a result, many times the same function is redesigned from one application to another. Promoting reuse by ensuring macro interconnectivity is accomplished by using common buses for inter-macro communications. To that end, the IBM CoreConnect architecture, for example, provides three buses for interconnecting cores, library macros, and custom logic. These buses are the Processor Local Bus (PLB), On-chip Peripheral Bus (OPB) and Device Control Register (DCR) Bus. Other chip vendors may have similar SOC core architectures, for example the Advanced Microcontroller Bus Architecture (AMBA) commercially available from ARM Ltd.
FIG. 1 illustrates how the prior art CoreConnect architecture is used to interconnect macros in the PowerPC 405 GP embedded controller. High-performance, high bandwidth blocks such as the Power PC 405 CPU core, PCI bridge and SDRAM controller reside on the PLB 102, while the OPB 101 hosts lower data rate peripherals. The daisy chain DCR bus 104 provides a relatively low-speed data path for passing configuration and status information between the PowerPC 405 CPU core and other on-chip macros. A PLB Arbiter 103 would handle contention between devices on PLB 102.
The CoreConnect architecture shares many similarities with other advanced bus architecture in that they both support data widths of 32 bits and higher, utilize separate read and write data paths and allow multiple masters. For example, the CoreConnect architecture and AMBA 2.0 now both provide high-performance features including pipelining, split transactions and burst transfers. Many custom designs utilizing the high-performance features of the CoreConnect architecture are available in the marketplace today.
The PLB and OPB buses provide the primary means of data flow among macro elements. Because these two buses have different structures and controls, individual macros are designed to interface to either the PLB or the OPB. Usually the PLB interconnects high bandwidth devices such as processor cores, external memory interfaces and DMA controllers. The PLB addresses the high-performance, low latency and design flexibility issues needed in the highly integrated SOC.
In any SOC design, the utilization of the on-chip bus structure is an important consideration. Efficient use of the bus produces better system throughput and response maps to real-time applications. It is therefore essential to architect means by which certain devices attached to the bus do not load or dominate the bus. The PLB has such a means designed into the architecture. This mechanism consists of logic designed into the bus masters to perform long variable-length burst transfers. Each master that attempts long burst transfers is required to monitor a signal, PLB_pendReq (PLB pending request). PLB_pendReq is signaled during long burst transfers which indicates if other master requests are active. Masters implement a programable latency timer such that once their burst transfer has begun on the data bus their timer starts counting down from the program value. When the latency timer reaches zero (times out), the master begins to sample the PLB_pendReq signal. If the PLB_pendReq signal is inactive, it indicates no other masters are requesting use of the bus and bursting may continue as long as PLB_pendReq remains inactive. If the latency timer has timed out and the PLB_pendReq is active, the bursting master must sample priority signals (e.g., PLB_pendPri(0:1)) to determine the relative request priority of other master(s) with the requests which are active. If a pending request priority of another master which is requesting the bus is equal to or greater than that of the bursting master, the bursting master must immediately terminate its burst transfer thereby allowing the pending master access to the bus.
In the above example, the PLB has two separate and completely independent data buses and burst control signals which allows for read and write data transfers to be performed simultaneously. Thus a condition may exist where, for example, a long read burst transfer is in progress and a higher priority write request is generated. Even though the write request would not affect the read transfer in any way, because it only needs access to the address and controls of the write data bus, the higher priority write request will cause a read bursting master to unnecessarily terminate its transfer if its latency timer has timed out. Thus the read master would have to again request the use of the read bus and arbitrate amongst the current pending requests. This has a negative effect on the overall system performance.
Therefore, there exists a need for a solution to the problem of interrupting a process on a bus because a higher priority process seeks access, especially in the case where those operations are read and write burst operations.
The present invention discloses a method and apparatus for managing a bus system with independent read and write buses. The internal bus structure, connecting high speed units internal to a microprocessor, usually has separate read and write buses. These buses are controlled by a master or arbiter that determines which device has control of the bus at a particular time. Different devices are assigned levels of priority which indicate their service priority in the case of bus contention. In the prior art, if a device was using the bus, for example a burst read or write, the device controlled the bus for the length of time indicated by its priority and the status of its latency timer. If it was a high priority device and another device of lower priority requested the bus, the lower priority device was placed in a queue dependent on its service priority.
The present invention separates the pending bus request signals, latency timers, and the pending bus priority signal for a read and a write operation. In embodiments of the present invention, a high priority device is granted a read request while the write bus may be granted to another device with a lower read request but a higher priority write request. The embodiments of the present invention allow bursting reads and writes to remain operational by a low priority device when a higher priority device requests the corresponding other bus operation.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.